Free Tutorials on Saturday, 25 July

The following tutorials will be held on the Fifth Floor of the San Francisco Marriott.

There is no charge for MSE registrants. You may attend more than one.
Please indicate your selection on the registration form.

08:30 -- 12:00 (Sierra H): Cypress -- Programmable System-on-Chip

08:30 -- 12:00 (Sierra I): NSF/Univ. of Arkansas -- Asynch Logic

08:30 -- 12:00 (Sierra J): Altera -- Using Altera Tools and FPGAs--Part I

12:00 -- 13:30: Lunch on your own

13:30 -- 17:00 (Sierra J): Altera -- Using Altera Tools and FPGAs--Part II

13:30 -- 17:00 (Sierra I): Mentor -- Synthesis with Catapult C

13:30 -- 15:00 (Sierra H): Synopsys -- Structured Methodology for Successful Low Power Verification

15:30 -- 17:00 (Sierra H): Synopsys -- Power-Performance Optimization of Digital Circuits


Fifth Floor