Abstract:

There is a wide range of cost/performance for implementing DSP algorithms
into silicon, especially when targeting diverse technologies like FPGAs and
ASICs. Finding the optimal implementation usually involves exploring the
tradeoffs between fully parallel vs. serial architectures and will be highly
dependent on the available resources, speed, and architecture of the
technology. This session will explore how some of the commmonly used
optimizations work and how they can be applied automatically to high-level
algorithm models using Synplicity's Synplify DSP tool. The seminar will
include examples in wireless communications and will benefit engineers who
are interested in:

- Methods to rapidly describe algorithms and explore speed/area
optimization tradeoffs

- Creating algorithms and IP that are easily portable and optimized
across vastly different FPGA technologies

Instructor: Chris Eddington

Chris is Senior Technical Marketing Manager for Synplicity's DSP products
with responsibility for product strategy, definition, and launch.
Prior to working at Synplicity he was Director of Technical Marketing at
Mellanox Technologies leading High Performance Networking marketing strategy
and 8x8 Inc. developing DSP microprocessors for multimedia applications.
Earlier work includes several IC design positions in the wireless communications
and networking industry. Chris holds a Masters Degree in Signal and
Image Processing from the University of Southern California.

Chris can be reached at chrise@synplicity.com