Advances in low power design techniques have resulted in the emergence of new classes of bugs that have escaped traditional verification techniques and led to functional failures in silicon. Drawing from the recently published Verification Methodology Manual for Low Power (VMM-LP), this tutorial will cover all aspects of a successful low power verification methodology. It will elaborate on the causes of low power bugs, how to detect and avoid them, enumerate the dos and don’ts of low power verification and give advice on creating the right verification plan. It will conclude with an introduction to the newly developed base classes that make the methodology reusable and scalable.
This tutorial is intended for anyone interested in or responsible for low power implementation and verification.
Instructor: Srikanth Jadcherla
Srikanth Jadcherla is a R&D Group Director in the Verification Group at Synopsys. He came to Synopsys in 2007 as part of the acquisition of ArchPro Design Automation, where he was founder and CTO. Prior to ArchPro, Jadcherla was an IC designer and architect at companies such as WSI, Intel, Jasmine and Synopsys. At Intel, Jadcherla worked on power management architectures ranging from servers to ultra mobile laptop platforms. Jadcherla received an Intel Achievement Award for his work on low power and is the author of 12 patents. He is an honorary green evangelist/technical advisor to various companies ranging from solar energy suppliers to real estate developers. Jadcherla holds a bachelor’s degree in electrical engineering from IIT-Madras in India, and a master’s degree in computational science and engineering from the University of California, Santa Barbara.
Srikanth Jadcherla can be contacted at sjadcher@synopsys.com
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Troy Wood is the University Alliances Manager for Synopsys.