C++ to Hardware: Exploiting high-level synthesis to accelerate design and optimize complex system-level algorithms using Catapult C Synthesis
Focusing too much time on coding a design implementation rather than doing algorithmic research for best hardware implementation ? Create your next hardware design using C++ and Mentor Graphics Catapult C Synthesis.
When writing pure C++, hardware designers focus on the functional intent of their application and not on timing and architectural information, which is abstracted away from the source description. With fewer details in the model, testbench development is also simplified. Once the C++ algorithm is created, the implementation specific details are automatically added during the C-to-RTL synthesis process through the use of constraints, eliminating error-prone manual intervention. This results in correct by construction RTL, which can automatically be verified using a push-button verification environment within Catapult. The RTL implementation of the C++ model is verified using the original C++ testbench, which eliminates the need to write pin-level interfacing and bit-timed RTL environments to verify the RTL blocks created during synthesis before moving to system integration.
The key benefits of high-level synthesis includes:
* ANSI C++ language synthesis with SystemC verification
* Dramatically reduces verification time through through automatic SystemC transaction level model (TLM) and testbench generation, allowing RTL tests using an untimed C++ testbench
* Create optimal hardware designs 10-100x faster than hand-coded methodologies
* Incremental refinement methodology enables maximum user control over implementation and latency/area/throughput results
* Automatically synthesize interfaces to external hardware
* Production-proven: Over 200 production ASIC tapeouts and hundreds of FPGA designs have successfully been deployed
In this sessions, attendees will learn the benefits of high-level synthesis techniques using Catapult C Synthesis, including:
* Modeling techniques for representing bit-accurate arithmetic in C++ through the use of the freely available "Algorithmic C" data types
* Taking algorithms written in "pure" ANSI C++ and turning them into high-performance hardware (RTL) implementations
* Exploring the architectural design space to see how algorithms can be quickly optimized for area, latency, and throughput, and how the resulting RTL code is created in minutes instead of the days or weeks required for VHDL or Verilog coding.
* Understanding the integrated verification environment to automatically validate the generated RTL functionality against the original C++ design without any need for recreating an HDL testbench, or deal with vector capture and synchronization.
A demonstration of Catapult synthesis and verification environment will also be given.
Catapult C is a high level synthesis tool for ASIC and FPGA hardware designers of wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements.
This tutorial is intended for anyone interested in learning how to use this tool in research or teaching.
Instructor: Thomas Bollaert
Thomas Bollaert is product marketing manager for high-level synthesis at Mentor Graphics. Prior to his current position, Thomas developed Mentor Graphics high-level synthesis product line in Europe during 5 years. He brings 14 years of experience in digital signal processing and system-level design practices, including a track record of helping electronic design teams move through strategic methodology changes, increasing competitiveness through improved design practices. Thomas started in the EDA industry at Cadence Design Systems, and then held positions at Innoveda and Summit Design. Thomas has an electronic engineering degree from ESIEE Paris.
He can be contacted at thomas_bollaert@mentor.com
Mentor Graphics Higher Education Program
Ian Burgess is the Development Manager of the Higher Education Program for Mentor Graphics.