This tutorial introduces Altera's technology and teaching materials developed specifically for use in Digital Logic and Computer Organization courses. We will give an overview of Altera's FPGA technology, and its application in an educational setting. We will concentrate on the use of Quartus II software and a hardware platform based on Altera's DE1/DE2 boards. Participants will have an opportunity to implement logic circuits on these boards, which were designed for use in educational environments.
We will demonstrate how Quartus II CAD software can be used to design and implement logic circuits that can be downloaded onto a DE1/DE2 board. The discussion will include the use of debugging facilities included in Quartus II software, such as the RTL (Register Transfer Level) Viewer and the SignalTap II Embedded Logic Analyzer.
Next, we will discuss how a computer system can be implemented on the DE1/DE2 board. This involves using the System-on-Programmable-Chip (SOPC) Builder tool and the Nios II soft-core processor. We will show how application programs written in either the Nios II assembly language or the C programming language can be compiled, downloaded and run. This will be done with the Altera Monitor Program, which provides the facilities for implementation and debugging of application programs.
We recommend that the attendees bring their own laptops. They should download and install software found at www.altera.com prior to the tutorial. In particular, attendees should download and install:
* Quartus II 9.0 web edition
* Nios II Embedded Design Suite 9.0
* Altera Monitor Program
The first two packages are available in the Download Center, which has a link at the top right corner of www.altera.com. The Altera Monitor Program is available on the University Program section of Altera's website. It can be found by opening the web page university.altera.com and clicking on the link called Design Software in the Educational Materials area of the web page.
We will provide Altera DE1 boards for use in the hands-on part of the tutorial.
At the end of the tutorial we will give away Altera DE1 boards to professors and instructors who attend the session.
Instructor: Tom Czajkowski
Tom received his PhD degree in Computer Engineering from the University of Toronto in 2008, researching CAD algorithms for Physical and Logic Synthesis for FPGAs. In 2008 he joined the Altera University Program, where he is responsible for CAD research and development of teaching materials. In 2008/2009 academic year he was also a lecturer at the University of Toronto, where he taught graduate and undergraduate courses.
Tom can be contacted at tczajkow@altera.com